1. Field of the Invention
The present invention relates to an FET buffer amplifier preferably applied to an input stage, a sample-and-hold circuit, sweep circuit or the like of measuring apparatuses such as an oscilloscope.
2. Description of the Prior Art
FIGS. 1 and 2 are circuit diagrams showing arrangements of conventional FET buffer amplifiers.
FIG. 1, an input FET Q1 is serially connected with a bias current FET Q2. In this example, n-channel depletion mode FETs are used as the input FET Q1 and bias current FET Q2, and the source of the input FET Q1 and the drain of the bias current FET Q2 are connected. The drain of the input FET Q1 is connected to a reference voltage source +V, and the gate thereof is connected to an input terminal 1 to which an input voltage Vin is applied. The gate and source of the bias current FET Q2 are connected to a voltage source -V to configure a current source. A voltage at the connecting point of the input FET Q1 and the bias current FET Q2 is produced via an output terminal 2 as an output voltage Vout.
In the buffer amplifier, the bias current, which is produced by the bias current FET Q2 whose gate and source are connected to the voltage source -V, flows through the input FET Q1. Consequently, the gate-to-source voltage of the input FET Q1 becomes approximately zero. As a result, a source follower circuit can be achieved having a small offset voltage across the input terminal 1 and output terminal 2, and small temperature drift.
On the other hand, in the circuit shown in FIG. 2, a resistor R3 is connected between the source of the input FET Q1 and the drain of the bias current FET Q2, and a resistor R4 is connected between the source and gate of the bias current FET Q2. These resistors are for accommodating variations in FETs.
FIGS. 3A-3D are diagrams illustrating waveforms of various portions of the circuit shown in FIG. 2. When the input voltage Vin is zero, then I.sub.Q1 =I.sub.Q2, where I.sub.Q1 and I.sub.Q2 are the currents flowing through the input FET Q1 and the bias current FET Q2, respectively. When the input voltage Vin changes from zero, the load current I.sub.RL flows as shown in FIG. 3C so that I.sub.Q1 =I.sub.Q2 +I.sub.RL. In other words, the current change .DELTA.I.sub.Q1 of the input FET Q1 is expressed as .DELTA.I.sub.Q1 =I.sub.RL. Accordingly, the output voltage Vout decreases by an amount indicated by oblique lines of FIG. 3B, which is expressed as (R3+source resistance of the input FET Q1).times..DELTA.I.sub.Q1. Here, the source resistance of the input FET Q1 is approximately equal to the reciprocal of the mutual conductance of the input FET Q1, and is usually on the order of several hundred ohms. Accordingly, the decrease in the output voltage Vout is a considerable amount.
To prevent such decrease in the output voltage, an emitter follower circuit is usually added as a post amplifier of the buffer amplifier in prior art.
The emitter follower circuit, however, has a direct current offset voltage across the input and output terminals in the form of a base-to-emitter voltage VBE. Since the offset voltage is susceptible to temperature drift, a circuit for correcting the drift is needed. This presents a problem that the entire arrangement of the buffer amplifier becomes more complicated.